PIC18F4455-I/ML【PDF 27/438 页】IC PIC MCU FLASH 12KX16 44QFN

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Sheet目录3826

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PIC18F2455/2550/4455/4550

DS39632E-page 120

2009 Microchip Technology Inc.

TABLE 10-5:

PORTC I/O SUMMARY

Pin

Function

TRIS

Setting

I/O

I/O Type

Description

RC0/T1OSO/

T13CKI

RC0

OUT

DIG

LATC<0> data output.

PORTC<0> data input.

T1OSO

OUT

ANA

Timer1 oscillator output; enabled when Timer1 oscillator enabled.

Disables digital I/O.

T13CKI

Timer1/Timer3 counter input.

RC1/T1OSI/

CCP2/UOE

RC1

OUT

DIG

LATC<1> data output.

PORTC<1> data input.

T1OSI

ANA

Timer1 oscillator input; enabled when Timer1 oscillator enabled.

Disables digital I/O.

CCP2(1)

OUT

DIG

CCP2 compare and PWM output; takes priority over port data.

CCP2 capture input.

UOE

OUT

DIG

External USB transceiver OE output.

RC2/CCP1/

P1A

RC2

OUT

DIG

LATC<2> data output.

PORTC<2> data input.

CCP1

OUT

DIG

ECCP1 compare and PWM output; takes priority over port data.

ECCP1 capture input.

P1A(3)

OUT

DIG

ECCP1 Enhanced PWM output, Channel A; takes priority over port

data. May be configured for tri-state during Enhanced PWM shutdown

events.

RC4/D-/VM

RC4

—(2)

TTL

PORTC<4> data input; disabled when USB module or on-chip

transceiver are enabled.

D-

—(2)

OUT

XCVR

USB bus differential minus line output (internal transceiver).

—(2)

XCVR

USB bus differential minus line input (internal transceiver).

—(2)

TTL

External USB transceiver VM input.

RC5/D+/VP

RC5

—(2)

TTL

PORTC<5> data input; disabled when USB module or on-chip

transceiver are enabled.

D+

—(2)

OUT

XCVR

USB bus differential plus line output (internal transceiver).

—(2)

XCVR

USB bus differential plus line input (internal transceiver).

—(2)

TTL

External USB transceiver VP input.

RC6/TX/CK

RC6

OUT

DIG

LATC<6> data output.

PORTC<6> data input.

OUT

DIG

Asynchronous serial transmit data output (EUSART module); takes

priority over port data. User must configure as output.

OUT

DIG

Synchronous serial clock output (EUSART module); takes priority

over port data.

Synchronous serial clock input (EUSART module).

Legend:

OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden

for this option)

Note 1:

Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).

RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is

determined by the USB configuration.

40/44-pin devices only.

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